74LVC3G17DP,125

74LVC3G17DP,125 is a triple non-inverting Schmitt trigger with 5V tolerant input. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V environments. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standards (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V). It is used in applications like wave and pulse shapers for highly noisy environments.

• Wide supply voltage range from 1.65V to 5.5V
• Overvoltage tolerant inputs to 5.5V, high noise immunity
• CMOS low-power consumption, latch-up performance exceeds 250mA
• Direct interface with TTL levels, IOFF circuitry provides partial power-down mode operation
• Input leakage current is ±0.1μA typ at (VI=5.5V or GND;VCC = 0V to 5.5V, -40°C to +85°C)
• Supply current is 0.1μA typ at (VI=5.5V or GND;IO = 0A;VCC = 1.65V to 5.5V, -40°C to +85°C)
• Input capacitance is 3.5pF typ at (-40°C to +85°C)
• Propagation delay is 5.6ns typical at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP8 package

Hinweise

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