74LVT126PW,118

74LVT126PW,118 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It features ESD protection (MIL STD 883 method 3015: exceeds 2000V, MM: exceeds 200V).

• Quad bus interface, 3-state buffers
• Wide supply voltage range from 2.7V to 3.6V
• Overvoltage tolerant inputs to 5.5V, BiCMOS high speed and output drive
• Direct interface with TTL levels, input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion and extraction permitted, no bus current loading when output is tied to 5V bus
• Power-up 3-state, IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 500mA per JESD 78 Class II Level B
• Complies with JEDEC standard JESD8C (2.7V to 3.6V)
• Operating temperature range from -40°C to +85°C, TSSOP14 package

Hinweise

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